1. Field of the Invention
The present invention relates to a method of controlling a double integral analog-to-digital converter (hereinafter referred to as a double integral A-D converter) in order to reduce the influence caused by the electric charge absorption property of an integrating capacitor.
2. Description of the Related Art
An arrangement of a conventional double integral A-D converter will be described with reference to FIG. 2.
The conventional double integral A-D converter comprises an integrator 4A having one input connected to an input terminal 1 to which an input signal is applied by way of a switch 2A, reference power supplies 3A, 3B having first and second reference voltages by way of switches 2C and 2D, an integrating capacitor 4B and a switch 2E disposed between the input and output of the integrator 4A, a comparator 5 connected to the output of the integrator 4A, a gate 7 having one input connected to an output of the comparator 5 and the other input connected to a clock generator by way of a switch 2F, a counter 8 connected to an output of the gate 7 and producing data for A-D conversion (hereinafter referred to as A-D converting data) such as A-D coverting start signal (hereinafter referred to as start signal) and a control circuit 9 for receiving the A-D converting data and controlling to turn on the switches 2A to 2F.
One cycle of operation of the double integral A-D converter requires three procedures or sequences.
The first sequence comprises the step of turning on the switches 2A and 2C so that the integrating capacitor 4B stores the electric charge corresponding to the sum of the first reference voltage V.sub.1 of the reference power supply 3A and an input signal applied to the input terminal 1. The second sequence comprises the steps of turning on the switch 2D and turning off the switches 2A and 2C so that the integrating capacitor 4B discharges the electric charge stored therein upon reception of the second reference voltage V.sub.2 of the reference power supply 3B so that the clock generator 6 supplies a clock for A-D conversion (hereinafter referred to as A-D converting clock) to the gate 7 and the comparator permits the A-D converting clock to be supplied from the gate 7 to the counter 8 during the period of the discharge of the integrating capacitor 4B. The third sequence comprises the step of turning on the switch 2E and turning off the switches 2D and 2F so that the integrating capacitor 4B can discharge the electric charge residual therein.
The operation of the conventional double integral A-D converter will be explained with reference to the timing diagram in FIG. 3.
In the diagram of FIG. 3(a), the abscissa represents time, and the ordinate represents electric charge stored in the integrating capacitor 4B. Denoted at Q.sub.1 is an absorbed electric charge caused by dielectric absorption phenomenon.
In the diagram of FIG. 3(b), an axis of ordinate represents current charged in or discharged from the integrating capacitor 4B in which denoted at I.sub.1 is a charging current generated by the reference voltage V.sub.1, I.sub.2 is a discharging current generated by the reference voltage V.sub.2, and I.sub.3 is a discharging current of the absorbing electric charge.
In FIG. 3(c), the ordinate represents the voltage which appeared at the anode and cathode of the integrating capacitor 4B.
In FIG. 3, the A-D conversion by integrating capacitor 4B is initiated at the time T.sub.0 when the analog input signal applied to the input terminal 1 is not subject to the A-D conversion.
The residual electric charge of the integrating capacitor 4B based on which the A-D conversion is initiated at the time T.sub.0 is mainly composed of the following components:
(a) the electric charge stored during the delay time counting from the detection of ground voltage by the comparator 5 to the switching off of the switch 2D by the control circuit 9, and
(b) the absorbed electric charge caused by the electric charge absorption property of the integrating capacitor 4B.
Although the residual electric charge (a) can be discharged for initiating A-D conversion in less than ten times as long as the time constant which is determined by the equation .tau.=CR wherein C is an electrostatic capacitance of the integrating capacitor 4B and R is a resistance generated when the switch 2E is turned on, the absorbed electric charge takes more than several seconds for initiating A-D conversion.
Consequently, when the A-D conversion is repeated in short cycles, the residual electric charge caused by the preceding A-D conversion may cause the A-D converting data error.
The operation of the conventional double integral A-D converter, in case that the A-D conversion is repeated, will be described with reference to FIG. 4.
In FIG. 4, the abscissa represents time and the ordinate of FIG. 4(a) represents the electric charge stored in the integrating capacitor 4B.
The ordinate of FIG. 4(b) represents the voltage which appears at the anode and cathode of the integrating capacitor 4B, and W.sub.11 through W.sub.13 represent voltage waveforms which appear when the integrator 4A carries out integration upon reception of the A-D conversion start signal.
The waveform W.sub.12 suffers less influence from the absorbed electric charge because the time T.sub.3 associated therewith is long, but W.sub.13 is greatly influenced by the absorbed electric charge because the time T.sub.3 associated therewith is short.
The influence caused by the absorbed electric charge of the integrating capacitor 4B on the A-D converting data is determined by the A-D conversion cycle and the amount of the electric charge stored during the time T.sub.1 for integrating the input signal in the preceding A-D conversion sequence. Consequently, if the A-D conversion is made in the same cycle and the range of the input signal is limited to some extent, the A-D converting data is always subjected to the constant influence caused by the absorbed electric charge.